Memory devices are known in the art and used in, among other things, virtually all microprocessor and digital signal processor applications. Static Random Access Memory (SRAM) is one type of memory favored in many applications because it is fast and easy to use relative to many other memory types. In addition, SRAM devices that use metal-oxide-semiconductor (MOS) technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These attributes make SRAM devices particularly desirable for battery-powered equipment, such as laptop computers and personal digital assistants.
The SRAM devices are often employed in the equipment as part of an Integrated Circuit (IC) that includes logic circuitry. To reduce failures in the equipment, manufacturers may test a percentage of manufactured ICs under normal and abnormal operating conditions. Standard test procedures for this functional testing have been developed that establish performance measurements of the ICs being tested to validate design and screen-out poor quality devices. Some standard procedures test the ICs at voltages lower or higher than a normal operating voltage (voltage extremes). During testing of the ICs, the SRAM devices must function properly to adequately evaluate the logic circuitry. Testing at a low voltage extreme while at room temperature, or low voltage testing, may be used to screen-out SRAM devices that may prove unreliable or simply fail at temperatures greater than room temperature, thus, preventing evaluation of the logic circuitry.
A typical SRAM device includes an array of six-transistor SRAM memory cells consisting of two p-channel “pull-up” transistors, two n-channel “pull-down” transistors and two access transistors, which are typically n-channel transistors. The strength of the p-doped and n-doped channels of the transistors affects the performance, including static noise margin (SNM) and trip voltage (measure of ability to Write into an SRAM) of the SRAM memory cells as a whole.
SNM and trip voltage (so-called “Vtrip”) are parameters associated with the SRAM devices that may degrade during low voltage testing resulting in failure of the SRAM devices. Typically, a high SNM and trip voltage are desired cell characteristics of an SRAM device. A high SNM is desired for circuit stability and a high trip voltage is desired for adequate data write speed. If SNM is too low, READ operations may be disrupted and if trip voltage is too low, WRITE operations may be disrupted.
The SNM, however, may be less at the normal operating voltage and an elevated temperature than at a low voltage testing voltage and room temperature. Thus, the low voltage testing may result in an alpha error since a worst case condition for the SNM may not be provided during testing. Some SRAM devices, therefore, may be deemed operationally sufficient though not truly tested at worst conditions.
Besides SNM, the low voltage testing voltage may be limited by other functions, such as the trip voltage or logic functionality. The trip voltage, however, is a strong function of voltage that may degrade as operating voltage is decreased. Thus, the low voltage testing may result in a beta error since the trip voltage may degrade below a worst case condition due to a reduced voltage compared to the normal operating voltage and prevent an effective screen for other functions such as SNM.
Accordingly, what is needed in the art is an improved testing method and test apparatus that, during a low voltage test, effectively screens SRAM devices and maintains functionality of the SRAM devices to enable testing of associated logic.